Principal Analog IC Layout Engineer

In breve

NXP Semiconductors is looking for a Principal Analog IC Layout Engineer to join its Central Layout Group, which supports the Power Energy Business Line and focuses on Automotive Power Solutions. The team provides physical‑implementation expertise for complex mixed‑signal and power‑management ICs used in automotive and industrial applications, working closely with design, verification, packaging, test and product engineering across NXP's global R&D network. In this senior technical role you will lead the layout of sophisticated mixed‑signal and power‑management products, from concept through tape‑out. Responsibilities include defining floor‑planning strategies, acting as the go‑to expert for layout methodologies and flows, and supporting critical technical decisions that affect project execution and product quality. You will also drive top‑level layout development, anticipate risks, propose mitigations, ensure compliance with design standards, and contribute to project planning, reviews and milestone delivery. A key part of the position is to improve productivity and consistency across the organization. You will contribute to methodology, automation and tool enhancements, promote reuse and standardisation, and share lessons learned with worldwide teams. Collaboration is essential: you will work with design, verification, packaging, test, product engineering, reliability and technology groups, help resolve cross‑disciplinary issues, and mentor other layout engineers. The role requires a Master's degree in Electrical Engineering, Electronics, Physics or Microelectronics and extensive experience in analog IC layout. You must have expert knowledge of Cadence Virtuoso, Calibre and physical verification flows, as well as strong expertise in mixed‑signal, BCD and high‑voltage technologies. Proven leadership of complex top‑level layout activities, a solid grasp of layout quality, reliability and manufacturability, excellent communication and stakeholder‑management skills, and fluency in English are also mandatory. Preferred experience includes automotive semiconductor work, layout automation and scripting (SKILL, Python, TCL), multi‑technology exposure, methodology‑improvement leadership and experience in international R&D settings. The position is based in Italy, with a gross annual base salary range of €61,000‑€83,900, plus potential incentives, equity and a competitive benefits package. What the role asks for: - Master Degree in Electrical Engineering, Electronics, Physics or Microelectronics - Extensive experience in Analog IC Layout development - Expert knowledge of Cadence Virtuoso, Calibre and verification flows - Strong expertise in mixed‑signal, BCD and High Voltage technologies - Proven experience leading complex top‑level layout activities - Strong understanding of layout quality, reliability and manufacturability - Excellent communication and stakeholder management skills - Fluent English - Nice-to-have: Experience with automotive semiconductor products - Nice-to-have: Layout automation and scripting (SKILL, Python, TCL) - Nice-to-have: Multi‑technology expertise - Nice-to-have: Experience driving methodology improvements across organizations - Nice-to-have: Experience in international R&D organizations